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19-2575; Rev 0; 10/02
One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver
General Description
The MAX9323 low-skew, low-jitter, clock and data driver distributes one of two single-ended LVCMOS inputs to four differential LVPECL outputs. A single logic control signal (CLK_SEL) selects the input signal to distribute to all outputs. The device operates from 3.0V to 3.6V, making the device ideal for 3.3V systems, and consumes only 25mA (max) of supply current. The MAX9323 features low 150ps part-to-part skew, low 11ps output-to-output skew, and low 1.7ps RMS jitter, making the device ideal for clock and data distribution across a backplane or board. All outputs are enabled and disabled synchronously with the clock input to prevent partial output clock pulses. The MAX9323 is available in space-saving 20-pin TSSOP and ultra-small 20-pin 4mm 4mm thin QFN packages and operates over the extended (-40C to +85C) temperature range. The MAX9323 is pin compatible with Integrated Circuit Systems' ICS8535-01. o 1.7psRMS Added Random Jitter o 150ps (max) Part-to-Part Skew o 11ps Output-to-Output Skew o 450ps Propagation Delay o Pin Compatible with ICS8535-01 o Consumes Only 25mA (max) Supply Current (50% Less than ICS8535-01) o Synchronous Output Enable/Disable o Two Selectable LVCMOS Inputs o 3.0V to 3.6V Supply Voltage Range o -40C to +85C Operating Temperature Range
Features
MAX9323
Ordering Information
PART MAX9323EUP TEMP RANGE -40C to +85C PIN-PACKAGE 20 TSSOP
Applications
Precision Clock Distribution Low-Jitter Data Repeater Data and Clock Driver and Buffer Central-Office Backplane Clock Distribution DSLAM Backplane Base Station Hubs
MAX9323ETP* -40C to +85C 20 Thin QFN-EP** *Future product--Contact factory for availability. **EP = Exposed paddle.
Functional Diagram and Typical Operating Circuit appear at end of data sheet.
Pin Configurations
CLK_SEL CLK_EN GND Q0 17 Q0 16 GND 1 CLK0 1 N.C. 2 CLK1 3 N.C. 4 N.C. 5 15 VCC 14 Q1 CLK_EN 2 CLK_SEL 3 CLK0 4 N.C. 5 12 Q2 11 Q2 CLK1 6 N.C. 7 N.C. 8 6 N.C. 7 VCC 8 Q3 9 Q3 10 VCC N.C. 9 VCC 10 12 Q3 11 Q3 20 Q0 19 Q0 18 VCC 17 Q1
TOP VIEW
20
19
18
MAX9323
**EXPOSED PADDLE
13 Q1
MAX9323
16 Q1 15 Q2 14 Q2 13 VCC
THIN QFN-EP** (4mm x 4mm)
**CONNECT EXPOSED PADDLE TO GND.
TSSOP
________________________________________________________________ Maxim Integrated Products
1
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One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver MAX9323
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V Q_, Q_, CLK_, CLK_SEL, CLK_EN to GND .....................................-0.3V to (VCC + 0.3V) Continuous Output Current .................................................50mA Surge Output Current........................................................100mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 11mW/C)..............................879.1mW 20-Pin 4mm 4mm Thin QFN (derate 16.9mW/C)...1349.1mW Junction-to-Ambient Thermal Resistance in Still Air 20-Pin TSSOP ............................................................+91C/W 20-Pin 4mm 4mm Thin QFN.................................+59.3C/W Junction-to-Case Thermal Resistance 20-Pin TSSOP ............................................................+20C/W 20-Pin 4mm 4mm Thin QFN......................................+2C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, outputs terminated with 50 1% to (VCC - 2V), CLK_SEL = VCC or GND, CLK_EN = VCC, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25C.) (Notes 1, 2, and 3)
PARAMETER SYMBOL CONDITIONS CLK0, CLK1 CLK_EN, CLK_SEL CLK0, CLK1 CLK_EN, CLK_SEL MIN 2 2 0 0 -5 -5 -150 4 VCC 1.4 VCC 2.0 0.6 VCC 1.0 VCC 1.7 0.85 25 TYP MAX VCC VCC 1.3 0.8 150 +5 +5 UNITS
INPUTS (CLK0, CLK1, CLK_SEL, CLK_EN) Input High Voltage Input Low Voltage Input High Current Input Low Current Input Capacitance OUTPUTS (Q_, Q_) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage SUPPLY Supply Current (Note 5) ICC mA VOH VOL VOD Figure 1 Figure 1 Figure 1, VOD = VOH - VOL V V V VIH VIL IIH IIL CIN Figure 1 Figure 1 V V A A pF
CLK0, CLK1, CLK_SEL = VCC CLK_EN = VCC CLK0, CLK1, CLK_SEL = GND CLK_EN = GND CLK0, CLK1, CLK_SEL, CLK_EN (Note 4)
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One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, outputs terminated with 50 1% to (VCC -2V), fIN < 266MHz, input duty cycle = 50%, input transition time = 1.1ns (20% to 80%), VIH = VCC, VIL = GND, CLK_SEL = VCC or GND, CLK_EN = VCC, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25C.) (Note 4)
PARAMETER Switching Frequency Propagation Delay Output-to-Output Skew Part-to-Part Skew Output Rise Time Output Fall Time Output Duty Cycle Added Random Jitter Added Jitter (Note 9) SYMBOL fMAX tPHL, tPLH tSKOO tSKPP tR tF ODC tRJ tAJ fIN = 266MHz, clock pattern (Note 9) VCC = 3.3V with 25mV superimposed sinusoidal noise at 100kHz CONDITIONS VOH - VOL 0.6V VOH - VOL 0.3V CLK0 or CLK1 to Q_, Q_, Figure 1 (Note 6) (Note 7) (Note 8) 20% to 80%, Figure 1 80% to 20%, Figure 1 100 100 48 203 198 50 1.7 MIN 266 1500 100 450 600 30 150 300 300 52 3 10 TYP 800 MAX UNITS MHz ps ps ps ps ps % ps(RMS) ps(P-P)
MAX9323
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
Measurements are made with the device in thermal equilibrium. Positive current flows into a pin. Negative current flows out of a pin. DC parameters are production tested at TA = +25C and guaranteed by design over the full operating temperature range. Guaranteed by design and characterization. Limits are set at 6 sigma. All pins open except VCC and GND. Measured from the 50% point of the input to the crossing point of the differential output signal. Measured between outputs of the same part at the differential signal crosspoint for a same-edge transition. Measured between outputs of different parts at the differential signal crosspoint under identical conditions for a same-edge transition. Note 9: Jitter added to the input signal.
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One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver MAX9323
Typical Operating Characteristics
(VCC = 3.3V, outputs terminated to (VCC - 2V) through 50, CLK_SEL = VCC or GND, CLK_EN = VCC, TA = +25C.)
OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY
MAX9323 toc01
SUPPLY CURRENT vs. TEMPERATURE
14.0 13.5 SUPPLY CURRENT (mA) 13.0 12.5 12.0 11.5 11.0 10.5 10.0 -40 -15 10 35 60 85 TEMPERATURE (C) 800 700 OUTPUT AMPLITUDE (mV) 600 500 400 300 200 100 0 0
200 400 600 800 1000 1200 1400 1600 FREQUENCY (MHz)
OUTPUT RISE/FALL TIME vs. TEMPERATURE
MAX9323 toc03
PROPAGATION DELAY vs. TEMPERATURE
490 PROPAGATION DELAY (ps) 480 470 460 450 440 430 420 410 400 tPHL tPLH
MAX9323 toc04
230 220 OUTPUT RISE/FALL TIME (ps) 210 200 190 180 170 160 150 140 -40 -15 10 35 60 tF tR
500
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
4
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MAX9323 toc02
One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver
Pin Description
PIN TSSOP 1 QFN 18 NAME GND FUNCTION Ground. Provide a low-impedance connection to the ground plane. Synchronous Output Enable. Connect CLK_EN to VCC or leave floating to enable the differential outputs. Connect CLK_EN to GND to disable the differential outputs. When disabled, Q_ asserts low and Q_ asserts high. An internal 51k pullup resistor to VCC allows CLK_EN to be left floating. Clock Select Input. Connect CLK_SEL to VCC to select the CLK1 input. Connect CLK_SEL to GND or leave floating to select the CLK0 input. Only the selected CLK_ signal is reproduced at each output. An internal 51k pulldown resistor to GND allows CLK_SEL to be left floating. LVCMOS Clock Input. When CLK_SEL = GND, each set of outputs differentially reproduces CLK0. An internal 51k pulldown resistor to GND forces the outputs (Q_, Q_) to differential low when CLK0 is left open or at GND, CLK_SEL = GND, and the outputs are enabled. No Connect. Not internally connected. LVCMOS Clock Input. When CLK_SEL = VCC, each set of outputs differentially reproduces CLK1. An internal 51k pulldown resistor to GND forces the outputs (Q_, Q_) to differential low when CLK1 is left open or at GND, CLK_SEL = VCC, and the outputs are enabled. Positive Supply Voltage. Bypass VCC to GND with three 0.01F and one 0.1F ceramic capacitors. Place the 0.01F capacitors as close to each VCC input as possible (one per VCC input). Connect all VCC inputs together, and bypass to GND with a 0.1F ceramic capacitor. Inverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50 1% resistor. Noninverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50 1% resistor. Inverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50 1% resistor. Noninverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50 1% resistor. Inverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50 1% resistor. Noninverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50 1% resistor. Inverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50 1% resistor. Noninverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50 1% resistor.
MAX9323
2
19
CLK_EN
3
20
CLK_SEL
4 5, 7, 8, 9 6
1 2, 4, 5, 6 3
CLK0 N.C. CLK1
10, 13, 18 11 12 14 15 16 17 19 20
7, 10, 15 8 9 11 12 13 14 16 17
VCC Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0
Detailed Description
The MAX9323 low-skew, low-jitter, clock and data driver distributes one of two single-ended LVCMOS input signals to four differential LVPECL outputs. An input multiplexer allows selection of one of the two input signals. The output drivers operate at frequencies up to 1.5GHz. The MAX9323 operates from 3.0V to 3.6V, making it ideal for 3.3V systems.
select CLK0. Connect CLK_SEL to VCC to select CLK1. CLK0 and CLK1 are pulled to GND through internal 51k resistors, when not connected.
CLK_EN Input
CLK_EN enables/disables the differential outputs of the MAX9323. Connect CLK_EN to VCC to enable the differential outputs. The (Q_, Q_) outputs are driven to a differential low condition when CLK_EN = GND. Each differential output pair disables following successive rising and falling edges on CLK_, after CLK_EN connects to GND. Both a rising and falling edge on CLK_ are required to complete the enable/disable function (Figure 2).
Data Inputs
Single-Ended LVCMOS Inputs
The MAX9323 accepts two single-ended LVCMOS inputs (CLK0 and CLK1, Figure 1). An internal reference (VCC/2) provides the input thresold voltage for CLK0 and CLK1. CLK_SEL selects the CLK0 input or CLK1 input to be converted to four differential LVPECL signals (see Table 1). Connect CLK_SEL to GND to
CLK_SEL Input
CLK_SEL selects which single-ended LVCMOS input signal is output differentially as four LVPECL signals. Connect CLK_SEL to GND to select the CLK0 input.
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One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver MAX9323
VIH CLK0/CLK1 50% OF CLK INPUT VIL
Q_ VOH VOD VOL Q_ tPLH tPHL
80% Q_ - Q_ DIFFERENTIAL OUTPUT WAVEFORM 20%
80% 0V (DIFFERENTIAL) tR tF 20%
Figure 1. MAX9323 Clock Input-to-Output Delay and Rise/Fall Time
CLK0 OR CLK1
DISABLED CLK_EN
ENABLED
Q_
Q_
Figure 2. MAX9323 CLK_EN Timing Diagram
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One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver MAX9323
Table 1. Control Input Table
INPUTS CLK_EN 0 0 1 1 CLK_SEL 0 1 0 1 SELECTED SOURCE CLK0 CLK1 CLK0 CLK1 Q0-Q3 Disabled, pulled to logic low Disabled, pulled to logic low Enabled Enabled OUTPUTS Q0-Q3 Disabled, pulled to logic high Disabled, pulled to logic high Enabled Enabled
Connect CLK_SEL to VCC to select the CLK1 input. An internal 51k pulldown resistor to GND allows CLK_SEL to be left floating.
Applications Information
Output Termination
Terminate both outputs of each differential pair through 50 to (VCC - 2V) or use an equivalent Thevenin termination. Use identical termination on each output for the lowest output-to-output skew. Terminate both outputs when deriving a single-ended signal from a differential output. For example, using Q0 as a single-ended output requires termination for both Q0 and Q0. Ensure that the output currents do not violate the current limits as specified in the Absolute Maximum Ratings table. Observe the device's total thermal limits under all operating conditions.
ance and maximize common-mode noise immunity by maintaining the distance between differential traces and avoiding sharp corners. Minimize the number of vias to prevent impedance discontinuities. Minimize skew by matching the electrical length of the traces.
Chip Information
TRANSISTOR COUNT: 4430 PROCESS: BiCMOS
Functional Diagram
VCC VCC VCC
VCC
Power-Supply Bypassing
Bypass V CC to GND using three 0.01F ceramic capacitors and one 0.1F ceramic capacitor. Place the 0.01F capacitors (one per VCC input) as close to VCC as possible (see the Typical Operating Circuit). Use multiple bypass vias to minimize parasitic inductance.
51k CLK_EN
MAX9323
D Q CLK
Q0 Q0
Q1 CLK0 51k GND CLK1 51k GND CLK_SEL Q3 51k GND GND 1 Q2 0 Q1
Circuit Board Traces
Input and output trace characteristics affect the performance of the MAX9323. Connect each input and output to a 50 characteristic impedance trace to minimize reflections. Avoid discontinuities in differential imped-
Q2
Q3
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One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver MAX9323
Typical Operating Circuit
3.0V TO 3.6V 0.01F 0.1F 0.01F 0.01F
VCC
VCC
VCC Q0 Q0
ZO = 50
MAX9323
CLK_SEL Q1 Q1 CLK0 CLK1 Q2 Q2 ON CLK_EN OFF Q3 Q3 GND
ZO = 50 50 ZO = 50 50 LVPECL RECEIVER
VCC - 2V ZO = 50 ZO = 50
ZO = 50 ZO = 50
ZO = 50
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One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9323
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
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One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver MAX9323
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
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One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX9323
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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